VLSI Physical Design & Timing Analysis Course | IIT Roorkee Prof. Bishnu Prasad Das
Course Details
| Exam Registration | 1634 |
|---|---|
| Course Status | Ongoing |
| Course Type | Elective |
| Language | English |
| Duration | 12 weeks |
| Categories | Electrical, Electronics and Communications Engineering, VLSI design |
| Credit Points | 3 |
| Level | Undergraduate/Postgraduate |
| Start Date | 19 Jan 2026 |
| End Date | 10 Apr 2026 |
| Enrollment Ends | 02 Feb 2026 |
| Exam Registration Ends | 20 Feb 2026 |
| Exam Date | 19 Apr 2026 IST |
| NCrF Level | 4.5 — 8.0 |
Master the Art of Chip Design: A Deep Dive into VLSI Physical Design with Timing Analysis
The world runs on semiconductors. From smartphones to satellites, every advanced electronic system hinges on the intricate, microscopic world of Very-Large-Scale Integration (VLSI) chips. The journey from a conceptual circuit diagram to a manufacturable silicon chip is a complex ballet of engineering, dominated by two critical pillars: Physical Design and Timing Analysis. Mastering these is essential for anyone aspiring to shape the future of electronics.
We are excited to present a definitive 12-week course, "VLSI Physical Design with Timing Analysis," designed to equip you with the foundational and advanced knowledge required to navigate this challenging field. Guided by an esteemed expert from the Indian Institute of Technology Roorkee, this course offers a unique blend of theoretical depth and practical, hands-on experience with industry-standard open-source tools.
Your Guide: Learn from an Industry-Academia Expert
This course is meticulously crafted and delivered by Prof. Bishnu Prasad Das, an Associate Professor in the Department of Electronics and Communication Engineering at IIT Roorkee. Prof. Das brings a wealth of global research and practical experience to the classroom:
- Ph.D. from IISc Bangalore in Electronics Design and Technology.
- International Research Stints at Carnegie Mellon University (USA), Kyoto University (Japan), and Tokyo Institute of Technology (Japan).
- Current Research focuses on cutting-edge areas like in-memory computing, RISC-V processors, hardware security, and ultra-low-power design.
- Awarded the Young Faculty Research Fellowship by MeitY, Govt. of India, recognizing his contributions.
His unique perspective, bridging academic rigor and real-world research challenges, ensures the course content is both relevant and forward-looking.
Who Should Enroll in This Course?
This course is tailored for a wide audience seeking to build or enhance their expertise in VLSI chip implementation:
- Undergraduate Students: BTech students in ECE, CSE, EE, or related branches who have completed a basic digital electronics course.
- Postgraduate Students: MTech students specializing in VLSI, Microelectronics, or ECE.
- Research Scholars: Ph.D. students in ECE or CSE focusing on circuit design, architecture, or EDA.
- Industry Professionals looking to solidify their understanding of the physical design flow and timing closure.
Prerequisite: A fundamental course in Digital Logic Design is required to fully grasp the concepts.
Course Overview: From Partitioning to Timing Closure
This comprehensive course walks you through the entire VLSI physical design flow, with a special emphasis on ensuring your designs meet critical timing constraints. Over 12 weeks, you will explore:
- The Complete Physical Design Flow: Partitioning, Floorplanning, Placement, Clock Tree Synthesis, Global Routing, and Detailed Routing.
- Deep Dive into Static Timing Analysis (STA): Three dedicated weeks cover timing fundamentals, sequential circuit analysis, clock skew/jitter, advanced variations (OCV/CRPR), and crosstalk.
- Hands-On Tool Demos: Practical sessions with powerful open-source EDA tools including Qflow, Yosys, OpenSTA, and OpenROAD.
- Industry-Relevant Knowledge: Understanding standard cell libraries, PDK files, and low-power design considerations.
Detailed 12-Week Course Layout
| Week | Core Topic | Key Learning Points |
|---|---|---|
| 1 | Introduction & Algorithms | VLSI design flow, complexity analysis, graph algorithms for physical design. |
| 2-3 | Static Timing Analysis (STA) | Timing arcs, delay parameters, setup/hold checks, clock skew, jitter, OCV/CRPR. |
| 4 | Partitioning | Introduction to partitioning, KL Algorithm, Fiduccia-Mattheyses (FM) Algorithm. |
| 5 | Chip Planning (Floorplanning) | Floorplan representations, algorithms, pin assignment, power-ground routing. |
| 6 | Placement | Wirelength estimation, min-cut placement, placement algorithms, legalization. |
| 7 | Clock Routing | Clock Tree Synthesis (CTS) fundamentals and routing algorithms. |
| 8 | Global Routing | Optimization goals, rectilinear routing, connectivity graphs, Dijkstra’s algorithm. |
| 9 | Detailed Routing | Channel routing algorithms, switchbox routing, over-the-cell routing. |
| 10 | Advanced Timing | Timing in latches, time borrowing, crosstalk analysis, Statistical STA (SSTA). |
| 11 | Input Files & Libraries | Standard cell libraries, timing libraries (.lib), PDK files, low-power cells. |
| 12 | Open-Source Tool Flow | Hands-on with Qflow, Yosys, OpenSTA, and the complete OpenROAD physical synthesis flow. |
Essential Reference Books
To complement the lectures, the course references seminal texts in the field:
- "VLSI Physical Design: From Graph Partitioning to Timing Closure" by Kahng, Lienig, Markov, and Hu.
- "Algorithms for VLSI Physical Design Automation" by Naveed Sherwani.
- "Static Timing Analysis for Nanometer Designs" by J. Bhasker and Rakesh Chadha.
- "Advanced ASIC Chip Synthesis" by Himanshu Bhatnagar.
Unlock Your Career in VLSI
This course is directly relevant to the core R&D and product development cycles of all major semiconductor companies, including Intel, AMD, Qualcomm, Texas Instruments, Analog Devices, and STMicroelectronics. Proficiency in physical design and timing analysis is a highly sought-after skill, opening doors to roles in chip implementation, CAD engineering, and design verification.
Whether you are a student building your foundation or a professional aiming to upskill, "VLSI Physical Design with Timing Analysis" provides the structured knowledge and practical exposure needed to excel in the competitive and exciting world of chip design. Enroll today and take the first step towards mastering the craft that builds the digital future.
Enroll Now →